Posted by New Delhi: Cadence has launched a new chiplet partner ecosystem aimed at reducing engineering complexity and accelerating time to market for customers developing chiplet based designs for physical AI, data centre and high performance computing applications.
The Chiplet Spec to Packaged Parts chiplet partner ecosystem brings together a group of technology and intellectual property partners to deliver pre validated chiplet solutions based on the Cadence Physical AI chiplet platform. Initial partners include Arm, Arteris, eMemory, M31 Technology, Silicon Creations, Trilinear Technologies and silicon analytics company proteanTecs.
To support customer adoption, Cadence is collaborating with Samsung Foundry to build a silicon prototype demonstration of the platform using the Samsung Foundry SF5A process. The prototype will include pre integrated partner IP and is intended to help customers evaluate chiplet designs with lower risk and faster development cycles.
Cadence and Arm are extending their long standing collaboration as part of the expanding chiplet ecosystem. Cadence will use the Arm Zena Compute Subsystem and other Arm IP to enhance its Physical AI chiplet platform and Chiplet Framework. The companies said the solutions will support demanding edge AI workloads in automotive systems, robotics and drones, while also enabling standards based input output and memory chiplets for cloud, data centre and high performance computing environments.
“Cadence’s new chiplet ecosystem represents a significant milestone in chiplet enablement,” said David Glasco, VP of Compute Solutions Group, Cadence.
“Multi-die and chiplet-based architectures are increasingly critical to achieving greater performance and cost efficiency amid growing design complexity. Cadence’s chiplet solutions optimize costs, provide customisation flexibility and enable configurability,” added Glasco.
Further, “By combining our extensive IP and SoC design expertise with pre-integrated and pre-validated IP from our robust partner ecosystem, Cadence is accelerating the development of chiplet-based solutions and helping customers mitigate risk to quickly realize their chiplet ambitions with greater confidence,” informed Glasco.
Cadence has developed spec driven automation to generate chiplet framework architectures that combine Cadence and partner IP with chiplet management, security and safety features. Advanced software and a complete electronic design automation flow, including simulation with the Cadence Xcelium Logic Simulator and emulation with the Cadence Palladium Z3 Enterprise Emulation Platform support these architectures..
The company said the chiplet partner ecosystem follows industry standards to ensure interoperability, including alignment with the Arm Chiplet System Architecture and future OCP Foundational Chiplet System Architecture. Connectivity is supported through Universal Chiplet Interconnect Express IP, alongside protocol IP for interfaces such as LPDDR6, LPDDR5X, DDR5 MRDIMM, PCI Express 7.0 and HBM4.
Cadence said the new chiplet ecosystem will help customers adopt chiplet technologies with greater confidence while enabling more efficient and scalable computing systems.